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VLSI Projects

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  • Low-Power and Area-Efficient Carry Select Adder-2012
  • Design and Characterization of Parallel Prefix Adders using FPGAs -2011
  • Simulation of Image Encryption using AES Algorithm – 2011
  • An Autonomous Vector/Scalar Floating Point Coprocessor for FPGAs-2011
  • A FPGA IEEE-754-2008 DECIMAL64 FLOATING-POINT ADDER/SUBTRACTOR -2011
  • Implementation of Convolutional Encoder and Viterbi Decoder using Verilog HDL-2011
  • Design and Simulation of UART Serial Communication Module Based on VHDL-2011
  • Design of three-lift controller based on FPGA -2011
  • A Review on Power Optimization of Linear feed back shift register (LFSR) for Low Power BIST.- 2011
  • The Design of an 8-bit CISC CPU Based on FPGA-2011
  • Optimized Design of UART IP Soft Core based on DMA Mode-2010
  • Design of SHA-1 Algorithm based on FPGA-2010
  • Implementation of Non-Pipelined and Pipelined Data Encryption Standard (DES) Using Xilinx Virtex-6 FPGA Technology -2010
  • FPGA Implementation of Pipelined 2D-DCT and Quantization Architecture for JPEG Image Compression-2010
  • A New VLSI Architecture of Parallel Multiplier–Accumulator Based on Radix-2 Modified Booth Algorithm. -2010
  • Test data Compression using efficient bit mask and dictionary selection method-2010
  • FPGA Implementation of efficient FFT algorithm based on complex sequence-2010
  • Simple Traffic light Controller: A Digital System design product-2010
  • Implementation of FIR Filter on FPGA Using DAOBC Algorithm -2010
  • FPGA based implementation of high performance Architectural Low Level Power 32 bit RISC Core-2009
  • A Fast VLSI design of SMS4 Cipher based on twisted BDD s-box architecture-2009
  • A FPGA IEEE-754 2008 Decimal 64 Floating Point Multiplier-2009
  •  Design and implementation of  lossless high speed data compression and Decompression using VHDL
  • Design and implementation of Encryption module in DES for SECURITY using VERILOG
  • Design and implementation of  Decryption module in DES for SECURITY using VERILOG
  • Implementation of real time Candy mechanic using VHDL
  • Design and implementation of pattern generator for circuit under test using VERILOG
  • Efficient design of butterfly architecture for radix 8  fast Fourier transform using VHDL
  • Design and implementation of  Digital Code Lock using VHDL
  • Implementation of First in First out design  using VHDL
  • VLSI design of  Traffic Light Controller using VHDL
  • Design and implementation of  Encryption module for AES core using VERILOG
  • Design and implementation of  Decryption module for AES core using VERILOG
  • Design and implementation of Elevator Controller using VHDL
  • Design and implementation of  LFSR for low power applications using VERILOG
  • Design and implementation of  Serializer and deserializer  using VHDL
  • Implementation of  Frequency Distributor module using VHDL
  • Design and implementation of  Vending machine controller using VHDL
  • Design and implementation of  Finite impulse response filter using VHDL
  • VLSI design of 8 bit microprocessor implementation using VHDL
  • Design and implementation of  array multiplier in VERILOG
  • Design and implementation of  state machine controller
  • Design and implementation of  Content Addressable Memory using VHDL
  • Design and implementation of  House hold alarm system using VHDL
  • VLSI design of  Reduced Instruction Set Computer Processor core using VHDL
  • VLSI implementation of  Memory Core design using VHDL
  • Design and implementation of Random number Generator using VERILOG
  • Design and implementation of USB Transmitter
  • Design and implementation of Booth multiplier
  • Design and implementation of Wallace Tree multiplier
  • Performance evaluation of high speed and low power adders.
  • Design of an ATM  (Automated Teller Machine) Controller
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